As part of the OSVISE project, TUM and UzL performed a systematic literature review (SLR) on integrated circuit (IC) power modeling. Following is a short overview of our work, which has also been submitted to ACM Computing Surveys and the preprint version is available here and mediaTUM.
Recent Posts
Participation Chipdesign Germany Forum 2026
We presented our work in OSVISE at the Chipdesign Germany Forum 2026 in Dresden.
OSVISE Presentation at DE:Sign Workshop
We presented our work in OSVISE at the DE:Sign workshop Digital Verification organized by Chip Design Germany in Hanover.
Project Meeting Break-off Milestone
This week the project partners came together in Munich for the break-off milestone meeting.
Intro Chosys project
In this post, we explore Chosys. A project which brings together two important tools in the chip design ecosystem.
PlanV: Verilator Series - Constrained Randomization Structs
Enabling UVM Support in Verilator Series: Constrained Randomization Support for Structs
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PlanV: Verilator Series - Constrained Randomization Arrays
Enabling UVM Support in Verilator Series: Constrained Randomization Support for All Types of Arrays
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PlanV: Verilator Series - Basic Randomization
Enabling UVM Support in Verilator Series: Basic Randomization Support for Aggregate Data Types
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PlanV: Verilator Series - CI System
Enabling UVM Support in Verilator Series: Our CI System and Test Models
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PlanV: Verilator Series - UVM Support
Enabling UVM Support in Verilator - Part 1: Constraint Random if/else Constraint Support
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PlanV: Verilator Series - Monitor Issue Fix
OSVISE Verilator Series: Monitor Issue Fix in Verilator
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DI-OSVISE project started
The project has started today, so we will launch the activities in the next weeks and engage with the community. The official assignment of resources was delayed and it will take some weeks to be fully operational.