We presented our work in OSVISE at the DE:Sign workshop Digital Verification organized by Chip Design Germany in Hanover.
DE:Sign workshop Digital Verification
Chip Design Germany organized a workshop to enable an exchange between all the participants of projects funded within the DE:Sign initiative. The workshop took place at the Institute of Microelectronic Systems of Leibniz University Hannover.
After a welcome by Prof. Holger Blume the participants reported on the current status of the projects. A focus was the exchange of updates and usage of open-source tools to further align the work between the teams.
The team of Prof. Payá-Vayá from the Chair of Chip Design for Embedded Computing from TU Braunschweig reported on their work on PATARA and EIS-V. The startup MachineWare showed their work on virtual prototypes and shared their experience of handling open-source projects and business needs.
OSVISE
The OSVISE project was represented by Yannick Lavan from TU Darmstadt and Tobias Wölfel from HM. They gave an overview of the work in OSVISE in general as well as a status update. Both gave the participants a more detailed introduction into their respective focus areas within the OSVISE project. Yannick showed his work on improving simulation speeds for RISC-V instruction set extensions. Tobias gave an introduction to CIRCT and MLIR and the design verification with SystemVerilog assertions.
Outlook
Chip Design Germany will organize more workshops in the future. We are looking forward to more meetings that strengthen research collaboration and advance chip design development in Germany.